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 MM74HC251 8-Channel 3-STATE Multiplexer
September 1983 Revised February 1999
MM74HC251 8-Channel 3-STATE Multiplexer
General Description
The MM74HC251 8-channel digital multiplexer with 3STATE outputs utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power consumption of standard CMOS integrated circuits, it possesses the ability to drive 10 LS-TTL loads. The large output drive capability and 3-STATE feature make this part ideally suited for interfacing with bus lines in a bus oriented system. This multiplexer features both true (Y) and complement (W) outputs as well as a STROBE input. The STROBE must be at a low logic level to enable this device. When the STROBE input is HIGH, both outputs are in the high impedance state. When enabled, address information on the data select inputs determines which data input is routed to the Y and W outputs. The 74HC logic family is speed, function, as well as pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
s Typical propagation delay Data select to Y: 26 ns s Wide supply range: 2-6V s Low power supply quiescent current: 80 A maximum (74HC) s 3-STATE outputs for interface to bus oriented systems
Ordering Code:
Order Number MM74HC251M MM74HC251SJ MM74HC251MTC MM74HC251N Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
(c) 1999 Fairchild Semiconductor Corporation
DS005328.prf
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MM74HC251
Truth Table
Inputs Select C X L L L L H H H H
H = HIGH Logic Level, L = LOW Logic Level X = Irrelevant, Z = High Impedance (off) D0, D1. . . D7 = The level of the respective D input
Outputs Strobe S H L L L L L L L L Y Z D0 D1 D2 D3 D4 D5 D6 D7 W Z D0 D1 D2 D3 D4 D5 D6 D7
B X L L H H L L H H
A X L H L H L H L H
Logic Diagram
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MM74HC251
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW -0.5 to +7.0V -1.5 to VCC +1.5V -0.5 to VCC +0.5V 20 mA 25 mA 50 mA -65C to +150C
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 0 -40 VCC +85 V C 2 Max 6 Units V
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| 20 A Conditions
(Note 4)
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 TA = 25C Typ 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 0.5 8.0 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 5 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 10 160 Units V V V V V V V V V V V V V V V V A A A
VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA IIN IOZ ICC Maximum Input Current Maximum 3-STATE Leakage Current Maximum Quiescent Supply Current Strobe = VCC VOUT = VCC or GND VIN = VCC or GND IOUT = 0 A 6.0V 6.0V VIN = VCC or GND 4.5V 6.0V 6.0V 4.5V 6.0V
Note 4: For a power supply of 5V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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MM74HC251
AC Electrical Characteristics
VCC = 5V, TA = 25C, CL = 15 pF, tr = tf = 6 ns Symbol tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tPZH, tPZL tPZH, tPZL tPHZ, tPLZ tPHZ, tPLZ Parameter Maximum Propagation Delay A, B or C to Y Maximum Propagation Delay, A, B or C to W Maximum Propagation Delay, Any D to Y Maximum Propagation Delay, Any D to W Maximum Output Enable Time, W Output Maximum Output Enable Time, Y Output Maximum Output Disable Time W Output Maximum Output Disable Time Y Output RL = 1 k CL = 50 pF RL = 1 k CL = 50 pF RL = 1 k CL = 5 pF RL = 1 k CL = 5 pF 27 35 ns 26 40 ns 19 26 ns 19 27 ns 24 32 ns 22 29 ns 27 35 ns Conditions Typ 26 Guaranteed Limit 35 Units ns
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC 2.0V 4.5V 6.0V tPHL, tPLH Maximum Propagation Delay, A, B or C to W tPHL, tPLH Maximum Propagation Delay, any D to Y tPHL, tPLH Maximum Propagation Delay, any D to W tPZH, tPZL Maximum Output Enable Time W Output tPZH, tPZL Maximum Output Enable Time Y Output tPHZ, tPLZ Maximum Output Disable Time W Output tPHZ, tPLZ Maximum Output Disable Time Y Output tTHL, tTLH Maximum Output Rise and Fall Time CPD CIN Power Dissipation Capacitance (Note 5) (per package) Maximum Input Capacitance RL = 1 k RL = 1 k RL = 1 k RL = 1 k 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA = 25C Typ 90 31 26 95 32 27 70 27 23 75 29 25 45 21 18 45 21 18 60 29 25 60 30 26 30 8 7 110 5 10 10 10 205 41 35 205 41 35 195 39 33 185 37 32 150 30 26 145 29 25 220 44 37 195 39 33 75 15 13 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 256 51 44 256 51 44 244 49 41 231 46 40 188 38 33 181 36 31 275 55 46 244 49 41 95 19 16 300 60 51 300 60 51 283 57 48 268 54 46 218 44 38 210 42 36 319 64 54 283 57 48 110 22 19 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF Units
tPHL, tPLH Maximum Propagation Delay A, B or C to Y
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC.
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MM74HC251
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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MM74HC251
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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MM74HC251 8-Channel 3-STATE Multiplexer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.


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